DK-DEV-5SGXEA7N【PDF 319/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV52002

2014.01.07

Channel PLL Used as a CMU PLL (Transmitter PLL)

1-19

Bonded Configurations

The high-speed serial clock and low-speed parallel clock skew between channels and unequal latency in the

transmitter phase compensation FIFO contribute to transmitter channel-to-channel skew. In bonded channel

configurations the parallel clock is generated by a central clock divider for all channels, rather than using a

local clock divider for each transmitter channel. Also, the transmitter phase compensation FIFO in all bonded

channels shares common pointers and control logic generated in the central clock divider, resulting in equal

latency in the transmitter phase compensation FIFO of all bonded channels. The lower transceiver clock

skew and equal latency in the transmitter phase compensation FIFOs in all channels provide lower channel-

to-channel skew in bonded channel configurations.

Related Information

For more information about clocking or bonding, refer to the Transceiver Clocking in Stratix V Devices

Channel PLL Used as a CMU PLL (Transmitter PLL)

The channel PLL available in the PMA can be used as a CMU PLL. The CMU PLLs in channels 1 and 4 in

a transceiver block can also provide a clock to the other transceivers within the same block.

When you use the channel PLL as a CMU PLL, that particular channel cannot be used as a receiver; however,

that channel can be used as a transmitter in conjunction with a different transmitter PLL. If all transmitters

and receivers within the transceiver block are required, you must use an ATX PLL or a clock from another

transceiver block.

For the best performance based on the data rate and input clock frequency, all settings for the CMU PLL

and clock dividers are automatically chosen by the Quartus II software.

Figure 1-15: Channel PLL Configured as CMU PLL

Channel PLL

/2

LTR/LTD

Controller

Phase

Down

2 /

Recovered Clock

rx_serial_data

Detector

(PD)

Up

refclk

/N =

1, 2, 4, 8

(1)

Phase

Frequency

Detector

(PFD)

Up

Down

Charge Pump

&

Loop Filter

Voltage

Controlled

Oscillator

(VCO)

Lock

Detect

/L =

2, 4, 8

(1)

Serial Clock

pll_is_locked

/M =

1, 4, 5, 8, 10,

12,16, 20, 25

(1)

Note:

1. Not all combinations of /N, /M, and /L values are valid. The Quartus II software automatically chooses the optimal values.

Transceiver Architecture in Stratix V Devices

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